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| mic2150/mic2151 2-phase dual output pwm synchronous buck control ic micro lead frame and mlf are registered trademarks of amkor technology, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micre l.com general description the mic2150/1 are simple 2-phase dual-output synchronous buck control ics featuring small size and high efficiency. the ics implem ent pwm control at 500khz (mic2150) or 300khz (mic2151), with the outputs switching 180 out of phase. the result of the out-of-phase operation is 1mhz input ripple frequency with ripple current cancellation, minimizing the required input filter capacitance. a 1% output voltage tolerance allows the maximum level of system performance. internal drivers with adaptive gate drive allow the highest efficiency with the minimum external components. a dual threshold enable pin, matched soft-start pins, and a power good output are provided, allowing a high level of control. the mic2150/1 are available in the small size 4mm4mm 24-pin mlf ? package. the mic2150/1 has a junction operating range from ?40 c to +125 c. data sheets and support documentation can be found on micrel?s web site at www.micrel.com. applications ? multi-output power supplies with sequencing ? dsp, fpga, cpu and asic power supplies ? telecom and networking equipment ? servers features ? dual synchronous buck control ic with outputs switching 180 degree out-of-phase ? 4.5v to 14.5v input voltage range ? adjustable output voltages down to 0.7v ? 1% output voltage accuracy ? mic2150: 500khz pwm operation ? mic2151: 300khz pwm operation ? adaptive gate drive allows efficiencies over 95% ? adjustable current limit with no sense resistor - senses low-side mosfet current ? internal drivers allow 20a per phase ? power good output allow simple sequencing ? dual threshold enable pin ? independent programmable soft-start pins ? output over-voltage protection ? input uvlo ? works with ceramic output capacitors ? tiny 4mm4mm 24-pin mlf ? package ? junction temperature range of -40 c to +125 c _________________________________________________________________________________________________________________________ typical application august 2009 m9999-082809-a (408) 944-0800
micrel, inc. mic2150 august 2009 2 m9999-082809-a (408) 944-0800 ordering information part number frequency voltage junction temp. range lead finish package mic2150yml 500khz adj. ?40c to +125 c pb-free 4mm4mm 24-pin mlf ? MIC2151YML 300khz adj. ?40c to +125 c pb-free 4mm4mm 24-pin mlf ? pin configuration 24-pin mlf ? (ml) pin description pin number pin name pin function 1 bs1 boost 1(input): provides voltage for high -side mosfet driver 1. the gate drive voltage is higher than the source voltage by v dd minus a diode drop. 2 hsd1 high-side drive 1 (output): high curre nt output-driver for ext. high-side mosfet. 3 sw1 switch node 1(output): high curr ent output driver return for hsd1. 4 cs1 current sense 1 (input): current-limit comparator non-inverting input. the current limit is sensed across the low-si de fet during the on-time. current limit is set by the resistor in series with the cs1 pin. 5 ss1 soft-start, output 1(input): controls the tu rn-on time of the output voltage. active at power-up, enable and current limit recovery. 6 comp1 compensation 1 (input): pin for external compensation, channel 1. 7 agnd analog ground (signal): signal path return for fb, en, pgood, avdd, ss and comp. 8 fb1 feedback 1 (input): input to channel 1 error amplifier. regulates to 0.7v. 9 avdd analog supply voltage (input): connect ext. bypass capacitor. 10 fb2 feedback 2 (input): input to channel 2 error amplifier. regulates to 0.7v. 11 pgood power good (output): indicates channel 1 output and channel 2 output > 90% nominal. 12 comp2 compensation 2 (input): pin for external compensation, channel 2. micrel, inc. mic2150 august 2009 3 m9999-082809-a (408) 944-0800 pin number pin name pin function 13 ss2 soft-start, output 2(input): controls the tu rn-on time of the output voltage. active at power-up, enable and current limit recovery. 14 cs2 current limit 2 (input): current-limit co mparator non-inverting input. the current limit is sensed across the low-side fet dur ing the on time. current limit is set by the resistor in series with the cs2 pin. 15 sw2 switch node 2 (output): high curr ent output driver return for hsd2. 16 hsd2 high-side drive 2 (output): high curre nt output-driver for the high-side mosfet. 17 bs2 boost 2 (input): provides voltage for high- side mosfet driver 2. the gate drive voltage is higher than the source voltage by v dd minus a diode drop. 18 pgnd2 power ground 2. high current return for low-side driver 2 & cs2. 19 lsd2 low-side drive 2 (output): high-curre nt driver output for external mosfet. 20 vdd 5v internal linear regulator from v in (output): v dd is the ext. mosfet gate drive supply voltage and an internal supply bus for the ic. when v in is <5v, this regulator operates in drop-out mode. connect external bypass capacitor. 21 en enable (input): dual thres hold enable pin. logic low tu rns the ic off. exceeding lower threshold enables channel 1, exceeding higher threshold then enables channel 2. the dual threshold function allows the option of power up sequencing from a single en pin. both channels must be turned on and off together. the enable pin must be driven higher than 2.8v for proper operation. 22 vin supply voltage channel 1 (input): 4.5v to 14v 23 lsd1 low-side drive 1 (output): high-curre nt driver output for external mosfet. 24 pgnd1 power ground 1: high current return for low-side driver 1 & cs1. epad ep exposed pad (power): must make a full connection to the gnd plane to maximize thermal performance of the package. micrel, inc. mic2150 august 2009 4 m9999-082809-a (408) 944-0800 absolute maximum ratings (1) supply voltage (v in ) ........................................ ?0.3v to 15v bootstrap pin voltage (bst & hsd) ....................... v in + 6v fb, comp, ss, v dd , lsd & a vdd .................... ?0.3v to 6v cs, sw & en .................................................. ?0.3v to 15v power good (p good ) ........................................ av dd + 0.3v storage temperature (t s ).........................?65 c to +150 c lead temperature (solde ring 10 sec onds) ............... 260c esd rating (3) .............hbm = 2kv, mm = 200v, cdm = 2kv operating ratings (2) supply voltage (v in )................................... +4.5v to +14.5v output voltage ran ge................................ 0.7v to 0.83v in junction temperature range ............. ?40 c t j +125 c package thermal resistance mlf ? ( ja )..........................................................60 c/w mlf ? ( jc )............................................................6 c/w electrical characteristics (4) t j = 25c; v en = v in = 12v; unless otherwise specified. bold values indicate ?40 c t j +125 c parameter condition min typ max units v in , v en , v dd supply total supply current, pwm mode supply current v fb = 0.7v (both o/ps) (outputs switching but excluding ex ternal mosfet gate current.) 4.2 10 ma shutdown current v en = 0v 50 100 a v in uvlo start voltage v in rising 1.5 2.03 2.4 v v in uvlo stop voltage v in falling 1.5 2 2.4 v v in uvlo hysteresis 30 mv v dd uvlo start voltage v dd rising 3.0 3.3 3.6 v v dd uvlo stop voltage v dd falling 2.8 3.1 3.4 v v in uvlo hysteresis 200 mv v en threshold 1 0.8 1 1.2 v v en threshold 2 1.7 2 2.3 v v en hysteresis (each threshold) 30 mv internal bias voltages (v dd ) iv dd = -50ma 4.5 5 5.5 v v in = 6v to 14.5v 75 ma v dd load current v in = 5.5v 50 ma oscillator / pwm section mic2150 450 500 550 khz pwm frequency see design note (internal oscillator = 2x pwm frequency) mic2151 270 300 330 khz mic2150 80 % maximum duty cycle (each channel) mic2151 83 % minimum on-time (5,6) (each channel) 30 50 ns notes: 1. exceeding the absolute maximu m rating may damage the device. 2. the device is not guaranteed to f unction outside its operating rating. 3. devices are esd sensitive. hand ling precautions recommended. human body model, 1.5k in series with 100pf. 4. specification for packaged product only. 5. minimum on-time before automatic cycle skipping begins. see applications section. 6. guaranteed by design. micrel, inc. mic2150 august 2009 5 m9999-082809-a (408) 944-0800 parameter condition min typ max units regulation feedback voltage reference (each channel) 25 o c (each channel) ?40 c to +125 c 691 686 700 709 714 mv feedback bias current (each channel) 35 500 na output voltage line regulation (each channel) 0.03 % / v error amplifier (each channel) dc gain (6) 70 db output over voltage protection (each channel) v fb threshold (latches lsd high) 110 115 120 %nom delay blanking time 2 s soft-start internal soft-start source current (each channel) v ss = 1v 1.25 1 2 2.75 3 a soft-start source current matching between channels ? 30 0 30 % internal soft-start discharge current (each channel) during soft current limit 18 a current sense (each channel) cs over current trip point program current 170 200 230 a cs comparator sense threshold ?7 0 +7 mv power good v fb threshold 86 90 93 %nom pgood voltage low v in = 4.5v, v fb = 0 v; i pgood = 1ma 0.1 0.3 v output dynamic correction thresholds upper threshold, v fb_ovt (6) (relative to v fb ). +6.5 % lower threshold, v fb_uvt (6) (relative to v fb ). ?6.5 % gate drivers rise 23 ns rise/fall time into 3000pf fall 16 ns source 1.5 3 low-side drive resistance v in = 5v sink 1.5 2 source 1.5 3 high-side drive resistance v in = 5v sink 1.5 2 notes: 6. guaranteed by design. micrel, inc. mic2150 august 2009 6 m9999-082809-a (408) 944-0800 parameter condition min typ max units driver non-overlap time (adaptive) (6) 10 20 ns mic2150 40 60 ns driver non-overlap time between low-side off and high-side on (6) mic2151 70 100 ns notes: 6. guaranteed by design. micrel, inc. mic2150 august 2009 7 m9999-082809-a (408) 944-0800 typical characteristics 170 180 190 200 210 220 230 0 2 4 6 8 10 12 14 16 i cs (a) v in (v) cs pin current source vs v in 160 170 180 190 200 210 220 -40 -20 0 20 40 60 80 100 120 140 i cs (a) temperature (c) cs pin source current vs temperature v in = 14.5v 0 20 40 60 80 100 120 051015 input voltage (a) input voltage (v) input current vs. input voltage en = 0 0 1 2 3 4 5 6 7 8 0 5 10 15 20 input current (ma) input voltage (v) input current vs. input voltage en = 1.5v en = 2.5v enabled 4.4 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 -40 -20 0 20 40 60 80 100 120 v dd (v) temperature (c) vdd regulator vs. temperature v in = 7v v in = 6v i vdd = -50ma v in = 5v 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 0246810121416 enable threshold (v) input voltage (v) ch1 enable thresholds vs. input voltage ch1 on ch1 off 1.70 1.80 1.90 2.00 2.10 2.20 2.30 0246810121416 enable threshold (v) input voltage (v) ch2 enable thresholds vs. input voltage ch2 on ch2 off 110% 112% 114% 116% 118% 120% 122% 124% 126% 128% 130% 1 10 100 1000 trip voltage (% of v ref ) t pulse (s) ovp threshold vs. reaction time 81% 83% 85% 87% 89% 91% 93% 0246810121416 vfb for pg transition (% of v ref ) input voltage (v) power good thresholds vs. input voltage pg high pg low 60% 65% 70% 75% 80% 85% 90% 95% 0 5 10 15 20 efficiency (%) output current (a) efficiency vs. output current v in = 5v v in = 12v v in = 9v v out = 1.8v 60% 65% 70% 75% 80% 85% 90% 95% 0 5 10 15 20 efficiency (%) output current (a) efficiency vs. output current v in = 11v v in = 7v v out = 3.3v 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 duty cycle (%) v ss (v) max. duty cycle vs. v ss micrel, inc. mic2150 august 2009 8 m9999-082809-a (408) 944-0800 functional characteristics micrel, inc. mic2150 august 2009 9 m9999-082809-a (408) 944-0800 functional diagram micrel, inc. mic2150 august 2009 10 m9999-082809-a (408) 944-0800 functional description the mic2150 is a dual channel, synchronous buck controller built with the latest bicmos process for optimum speed and efficiency. both pwm channels operate 180 o out of phase with each other to minimize input capacitor ripple current and input noise. the control loop has two stages of regulation. during steady state to medium output dist urbances, the loop operates in fixed frequency, pwm mode while, during a large voltage disturbance (~6.5% nominal), the loop becomes hysteretic; meaning that for a short period, the switching mosfets are switched on continuously until the output voltage returns to its nominal level. this maximizes transient response for large load steps, while operating nominally in fixed frequency pwm mode. voltage mode control is used to allow for maximum flexibility and maintain good transient regulation. the operating voltage range is 4.5v to 14.5v and the output voltage can be set down to 0.7v. start-up surges are prevented using built in soft-start circuitry as well as resistor-less current sensing for overload protection. other protection features include uvlo, dual level enable thresholds, over voltage latch off protection, power good signal and dual level over current protection. theory of operation the output voltage of the converter is sensed at the inverting input of the error amp lifier. this is connected to v out via the two feedback resistors. the non-inverting input is connected to the internal 0.7v reference and the two are compared to produce an error voltage. this error voltage is then fed into the non-inverting input of the pwm comparator and compared to the 1.5v voltage ramp to create the pwm pulses. the pwm pulses propagate through to the mosfet drivers which drive the external mosfets and create the power switching waveform at the set dc (duty cycle). this is then filtered by a power inductor and low esr capacitor to produce the output voltage where v out dcv in . as an example, due to a load increase or an input voltage drop, the output voltage will instantaneously drop. this will cause micrel, inc. mic2150 august 2009 11 m9999-082809-a (408) 944-0800 the error voltage to rise, resulting in wider pulses at the output of the pwm comparator. the higher duty cycle power switching waveform will cause an associated rise in output voltage and will continue to rise until the feedback voltage is equal to the reference and the loop is again in equilibrium. it is necessary to reduce the bandwidth of this feedback loop in order to keep the system stable. this can result in relatively poor transient regulation performance. however, the mic2150 has a further hysteretic feedback loop which operates during large transients to reduce this effect. hysteretic mode is invoked when output voltage is detected to be 6.5% of its nominal level. if the input voltage step or output load step is large enough to cause a 6.5% deviation in v out , then the additional control loop functions to return the output voltage to its nominal set point in the fastest time possible. this is limited only by the time constant of the power inductor and output capacitor. this scheme is not used during normal operation because it creates a switching waveform whose frequency is dependant upon v in , passive component values and the load current. due to its large noise spectrum, it is only used during surges to keep switching noise at a known, fixed frequency. figure 1. hysteretic block diagram figure 2. hysteretic waveforms soft-start figure 3. soft-start at startup, the soft-start mosfet (ss fet ) is released and c ss starts to charge at the rate ss ss c 2a dt dv = . the pnp transistor?s emitter (c omp) starts to track v ss at that rate until it reaches the lower end of the pwm ramp waveform. this is around 950mv and is where switching pulses will begin to drive the power mosfets. this ramp continues on the comp pin until the loop reaches it?s regulation point which is dependant upon the duty cycle required for regulation and can be anywhere from 1.4v to 2.9v. v ss will however, continue to rise as the pnp base-emitter junction becomes reverse biased. during large over current or short circuit conditions, i.e., where current limit is detected and v out is <75% of nominal, the ss fet is momentarily switched on. this discharges c ss to ~150mv at which point, it re-starts the soft-start cycle once again. du ring soft-start, hysteretic comparators are disabled until the ? 6.5% comparator has been set. soft-start time = t1 + t2 where t1 = 0.9c ss /2a and t2 = 1.5v out c ss /(v in 2a) if the value of c comp is in the same magnitude as c ss , then there may be an additional delay associated as the error amplifier charges the c comp capacitor. current limit the mic2150 uses the r dson of the low-side mosfet to sense over current conditions. the lower mosfet is used as it displays much lower parasitic oscillations during switching then the upper mosfet. using the mosfet r dson is not the most accurate method of current measurement, but is an adequate method for circuit protection without adding additional cost and board space that would be taken by discrete current sense resistors. generally, the mic2150 current limit micrel, inc. mic2150 august 2009 12 m9999-082809-a (408) 944-0800 circuit acts to provide a fixed maximum output current until the resistance of the load is so low that the voltage across it is no longer within regulation limits. at this point (75% of nominal output volt age), hiccup current mode is initiated to protect down-stream loads from excessive current during hard short circuits and also reduces overall power dissipation in the pwm converter components during a fault. before hiccup current mode occurs, ?brick wall? current limiting is provided to prevent system shutdown or disturbance if the overload is only marginal. figure 4. overcurrent sensing during the normal operation of a synchronous buck regulator, as the lower mosfet is switched on, its drain voltage will become negative with respect to ground as the inductor current continues to flow from source to drain. this negative voltage is proportional to output load current, inductor ripple current and mosfet r dson . figure 5. current sensing waveforms the larger inductor current, the more negative vds becomes. this is utilized for t he detection of over current by passing a known fixed current source (200a) through a resistor r cs which sets up an offset voltage (i cs r cs ). when i sd (source to drain current)r dson is equal to this voltage, the mic2150?s over current trigger is set. this disables the next high-side gate drive pulse. after missing the high-side pulse, the over current (oc) trigger is reset. if, on the next low-side drive cycle, the current is still too high i.e., v cs is 0v, another high-side pulse is missed and so on. thus reducing the overall energy transferred to the output and v out starts to fall. as this successive missing of pulses results in an effectively lower switching frequency, power inductor ripple currents can get very high if left unlimited. the mic2150 therefore limits duty cycle during current limit to prevent currents building up in the power inductor and output capacitors. current-limit setting the current limit circuit responds to the peak inductor current flowing through the low-side fet. the value of r cs can be estimated with the ?simple? method or can be more accurately calculated by taking the inductor ripple current into account. the simple method current limit can be quickly estimated with the following equation: r cs = i out r dson(max) /200a. where: r dson is the maximum on-resistance of the low side fet at the operating junction temperature accurate method for designs where ripple current is significant when compared to i out or for low duty cycle operation, calculating the current setting resistor r cs should take into account that one is sensing the peak inductor current and that there is a blanking delay of approximately 100ns. figure 6. overcurrent-circuit waveform calculate peak switch current 2 i ii ripple out pk += where: lf )d1(v i s out ripple ? = now calculate the actual set point to allow for the 100ns delay. micrel, inc. mic2150 august 2009 13 m9999-082809-a (408) 944-0800 l tv ii dly out pk set ?= rcs can now be calculated using: mincs )max(dson set cs i ri r = where: d = duty cycle f s = switching frequency l = power inductor value t dly = current limit blanking time ~ 100ns i cs(min) = 180a example consider a 12v to 3.3v @ 5a converter with 0.5h power inductor and 90% efficiency at full load. %31 9.0v12 v3.3 efficiency v v d in out = = a11.9 h5.0khz500 )31.01(v3.3 i ripple = ? = a55.9 2 11.9 5i pk =+= a89.8 h5.0 ns100v3.3 a55.9i set = ?= = ? = 494 a180 m1089.8 r cs using the simple method here would result in a current limit point much lower than expected. this equation sets the minimum current limit point of the converter, but maximum will depend on the actual inductor value and r dson of the mosfet under current limit conditions. this could be in the region of 50% higher and should be considered to ensure that all the power components are within their thermal limits unless thermal protection is implemented separately. it is recommended to connect a 22pf capacitor from cs to agnd close to the pins of the ic to prevent adjacent channel switching noise from affecting the current limit behavior. over voltage protection if the voltage at the fb pin is detected to be 15% higher than nominal for >2s, the channel is stopped from switching immediately and latched off. switching can be re-started by taking en below the channel?s enable threshold and re-enabling or re-cycling power to the ic. power good output the power good output (pg) will go high only when both channel outputs are above 90% of their nominal set output voltage. if ch2 is disabled (en<2v), then pg will be low regardless of the state of ch1. if pg functionality is required for ch1 only, fb2 can be driven externally above 90% v ref to enable pg to operate on ch1 only. enable sometimes, at high currents, it is possible to see relatively large ground current peaks. these, in turn, can create voltage differentials between agnd points. in order to prevent these from affecting the converter operation, it is good practice to drive enable 0.5v higher than its maximum threshold i.e., >2.8v for both channels. v dd regulator the internal regulator provides a regulated 5v for supplying the analogue circuit power (av dd ) and the mosfet driver power from the input supply (v in ). while this is designed to operate in dropout at input voltages down to 3v, driver current will be limited while the v dd regulator is in dropout. it is therefore recommended that for v in ranges 5v to 7v, mosfet gate current should be kept to less than 50ma. the av dd supply should be connected to v dd through an rc filter to provide decoupling of the switching noise generated by the mosfet drivers taking large current steps from the v dd regulator. gate drivers the mic2150 is designed to drive both high-side and low-side n-channel mosfets to enable high switching speeds and the lowest possible losses. the high-side mosfet driver is supplied by bootstrapping the switching voltage at the drain of the lower mosfet to v dd . this provides the high-side mosfet with a constant vgs drive voltage equal to v dd . figure 7. high-side gate drive circuit and waveform when hsd goes high, this turns on the high-side mosfet and the sw node rises sharply. this is coupled through the bootstrap capacitor c bst and diode d bst becomes reverse biased. the mosfet gate is held at v dd - 0.5v above the source for as long as c bst remains charged. the bias curre nt of the high-side driver is <10ma so 100nf is sufficient to hold the gate voltage with minimal droop for the power stroke (high-side micrel, inc. mic2150 august 2009 14 m9999-082809-a (408) 944-0800 switching) cycle. there is a period when both driver outputs are held off (?dead time?) to prevent shoot-through current flowing. shoot-through current flows if both mosfets are on momentarily as the cycle?s crossover. this dead time must be kept to a minimum to reduce losses in the catch diode which could either be an external schottky diode placed across the lower mosfet or the internal schottky diode implemented in some mosfets. it is not recommended for high current designs, to rely on the intrinsic body diode of the power mosfet; these typically have large v f values and a slow reverse recovery characteristic which will add significant losses to the regulator. dependent on the mosfets used, the dead time could be required to be 150ns or 20ns. the mic2150 solves this vari ability issue by using an adaptive gate-drive scheme: i.e., bst = 10ma1.6s / 100nf = 160mv. for most applications, 220nf should be used to achieve an improved, lower droop. when the low-side driver turns on every switching cycle, any lost charge from c bst is replaced via d bst as it becomes forward biased. therefore minimum bst voltage is v dd ? 0.5v. the low-side driver is supplied directly from v dd at nominal 5v. adaptive gate drive when the high-side driver is turned off, naturally the inductor forces the voltage at the switching node (low- side mosfet drain) towards ground to keep current flowing. when the sw pin is detected to have reached 1.5v, the top mosfet can be assumed to be off and the low-side driver output is immediately turned on. there is also a short delay between the low-side drive turning off and the high-side driver turning on. this is fixed at ~60ns to 100ns to allow for large gate charge mosfets to be used. figure 8. adaptive gate drive diagram micrel, inc. mic2150 august 2009 15 m9999-082809-a (408) 944-0800 application information passive component selection guide inductor selection the inductor value is responsible for the ripple current which causes some proportion of the resistive losses in the power components. these losses are proportional to i ripple 2 . minimizing inductor ripple current can therefore reduce the rms current flowing in the power components and generally improve efficiency; this is achieved by choosing a larger value inductor. having said this, the actual value of inductance is realistically defined by space limitations, rms rating (i rms ) and saturation current (i sat ) of available inductors. if one looks at the newer flat wire inductors for example, these typically have higher i sat ratings than the i rms for lower values. also, as inductance value increases, these figures tend to get closer in value. this mirrors what happens in the converter with i sat analogous to the maximum peak switch current and i rms analogous to output current. as inductance increases, so i switch(pk) tends towards i out . this is a characteristic that makes these types of inductor optimal for use with high power buck converters such as mic2150. to determine the i sat and i rms rating of the inductor, we should start with a nominal value of ripple current. this should typically be no more than i out(max) /2 to minimize mosfet losses due to ripple current mentioned earlier. therefore: l min ~ ) efficiency v v 1( fi v 2 in out s out out ? i lrms > 1.04i out(max) i lsat > 1.25i out(max) any value chosen above l min will ensure these ratings are not exceeded. in considering the actual value to choose, one needs to look at the effect of rippl e on the other components in the circuit. the chosen induc tor value will have a ripple current of: i ripple ~ l v f )d1( out s ? this value should ideally be kept to a minimum, within the cost and size constraints of the design, to reduce unnecessary heat dissipation. output capacitor selection the output capacitor (c out ) will have the full inductor ripple current i ripplerms flowing through it. this creates the output switching noise which consists of two main components: out on ripple ripple pkpk c2 ti esr i vout + ? if therefore, the need is for low output voltage noise (e.g., in low output voltage converters), v out ripple can be directly reduced by increasing inductor value, output capacitor value or reducing esr. for tantalum capacitors, esr is typically >40m which usually makes loop stabilizat ion easier by utilizing a pole-zero (type ii) compensator. due to many advantages of multi-layer ceramic capacitors, among them, cost, size, ripple rating and esr, it can be useful to choose these in many cases. however, one disadvantage is the cv product. this is lower than tantalum. a mixture of one tantalum and one ceramic can be a good compro mise which can still utilize the simple type ii compensator. with ceramic output capacitors only, a double-pole, double-zero (type iii) compensa tor is required to ensure system stability. loop compensation is described in more detail later in the data sheet. ensure the rms ripple current rating of the capacitor is above i ripple 0.6 to improve reliability. input capacitor selection c in ripple rating for a single phase converter is typically i out /2 under worst case duty cycle conditions of 50%. this increases ~10% for a ripple current of i out /2. when both cycles are switching 180 out of phase, the ripple can reduce at dc <50% to: 21212 2 2 21 1 2 1 rmscin ddii2)d1(di)d1(di i ??+?= it is however, also advisable to closely decouple the power mosfets with 210f ceramic capacitors to reduce ringing and prevent noise related issues from causing problems in the layout of the regulator. the ripple rating of c in may therefore, be satisfied by these decoupling capacitors; allowing the use of perhaps one more ceramic or tantalum input capacitor at the input voltage node to decouple input noise and localize high di/dt signals to the regulator input. power mosfet selection the mic2150 drives n-chann el mosfets in both the upper and lower positions. this is because the switching speed for a given r dson in the n-channel device is superior to the p-channel device. there are different criteria for choosing the upper and lower mosfets and these criteria are more marked at lower duty cycles such as 12v to 1.8v conversion. in such an application, the upper mosfet is required to switch as quickly as possible to minimize transition micrel, inc. mic2150 august 2009 16 m9999-082809-a (408) 944-0800 losses (power dissipated during rise and fall times). conversely, the lower mosfet can switch slower, but must handle larger rms currents. when duty cycle approaches 50%, then the current carrying capability of the upper mosfet starts to become critical also and can sometimes benefit from ex ternal high current drivers to achieve the necessary switching speeds. mosfet loss = static loss + transition loss static loss (p s ) = i fetrms 2 r dson transition loss (p t ) = i out (tr + tf)v dsoff f s /2 where: tr + tf = rise time + fall time due to the worst case driver currents of the mic2150, the value of tr + tf simplifies to: tr + tf (ns) = qg (nc) qg can be found in the mosfet characteristic curves figure 9. mosfet gate charge characteristic v dsoff = voltage across mosfet when it is off i fetrms = () 3 lylylxlx d 2 2 +++ ix = i out ? i ripple /2 iy = i out + i ripple /2 d = t on f s d is not duty cycle (dc ~1.1v out /v in ) since it changes depending upon which mosfet one is calculating losses for. upper fet t on = dc/f s the lower mosfet is not on for the whole time that the upper mosfet is off due to the fixed 80ns high-side driver delay. therefore, ther e is an 80ns term subtracted from the lower fet on time equation. lower fet t on = (1 ? dc)/f s ? 80ns there are many mosfet packages available which have various values of therma l resistance and therefore, can dissipate more power if there is sufficient airflow or heat sink externally to remove the heat. however, for this exercise, one can assume a maximum dissipation of 1.2w per mosfet package. this can be altered if the final design has higher allowable package dissipation. look at lower mosfet first: 1.2w = p s + p t for the low-side fet, p t is small because vds off is clamped to the forward voltage drop of the schottky diode. therefore: r dson(max) ~1.2 / i fetrms 2 e.g. for 12v to 1.8v @ 10a r dson(max) <14m it is important to remember to use the r dson(max) figure for the mosfet at the maximum temperature to help prevent thermal runaway (as the temperature increases, the r dson increases). qgmax should be limited so that the low-side mosfet is off within the fixed 80ns delay before the high-side driver turns on. high-side mosfet: for the high-side fet, the losses should ideally be evenly spread between transit ion and static losses. use the center of the v in range to balance the losses. p t = 0.6 = i out qgvin mid f s /2 therefore: qgmax <0.62 / (i out x vin mid f s ) r dson is calculated similarly for the high-side mosfet: r dson(max) ~0.6 / i fetrms 2 using previous example: qgmax < 20nc r dson(max) < 35m note that these are maximum figures based upon thermal limits and are not targeted at the highest efficiency. selection of lower values is recommended to achieve higher efficiency designs. limits to watch out for: qg total <1500 nc/v in (<2500nc/v in for mic2151) ? total of both high-side and low-side mosfet qg values at v gs = 5v for both channels. ? e.g. @ v in(max) = 13.2v: qg total < 1500 / 13.2 = 114nc qg low <120nc (per lsd output) micrel, inc. mic2150 august 2009 17 m9999-082809-a (408) 944-0800 ? maximum turn on gate charge for each separate low- side mosfet to ensure proper turn off before high- side mosfet is switched on. output voltage setting the internal reference of the mic2150 is 0.7v nominal. therefore: v out = 0.7(r1 + r2)/r2 by setting r2 at <10k r1 = r2(v out ? 0.7)/0.7 the fb pin input offset current can be up to 500na. it is therefore recommended to use resistor values of less than 10k to improve output accuracy schottky diode and snubbing components when the high-side switch turns on, there is usually an overshoot and ringing associated with this fast edge. this is induced by perturbation of the tank circuit made up of a combination of trace and lead inductances and mosfet drain and other parasitic capacitances. this can cause unwanted emi and stress the driver circuitry if left un-damped. snubbing is recommended to reduce this ringing and acts to critically damp the natural ringing frequency of the tank circuit. technically, this can be achieved using a single resistance to dissipate the ringing energy. however, in practical terms, this would cause a dc power loss. therefore a series rc is used to act only on the edges of the waveform. there are several methods of calculating the ideal values for the rc. the approach presented here is to estimate a value of c then calculate the r. this is best left until the final layout and components are ava ilable as it then accounts for all the parasitic contri butors that cause the rising edge ringing. estimating c: with no snubbing, measure the frequency of ringing. this is fo. now add a capacitor that results in a ring frequency of fo/2. this is c snub . calculating r: r snub = 1/ c snub fo loop compensation the loop of a voltage mode, pwm buck converter contains 3 main blocks to be considered; the modulator, the power stage and the compensator. figure 10. loop compensation block diagram modulator this section turns the error signal from the error amplifier into a low impedance square wave with a pulse width proportional to the input. this section therefore includes the ramp, pwm comparator, drivers and mosfets. usually, at the moderate frequencies of the control loop, the delays which appear as a phase lag between the error amplifier output and the power stage are small, but significant in allowing a loop to become unstable. the average gain of this stage can therefore be assumed to be linear with a gain of v in /ramp and a phase shift less than 10 degrees. power stage this section is essentially t he inductor, output capacitors and load resistance. unlike the modulator, in the frequency range of the loop, this is a complex system and contains two poles (i.e., a ?40db/decade gain fall at 1/2. lc and a total 180 phase lag) and a zero ( i.e., a +20db/decade gain rise at 1/2 c.esr and a total 90 degree phase lead). if the zero created by the output capacitor?s esr is too high to affect the two poles of the lc, then it is possible to have the conditions for an unstable loop without compensation. in general, there are two types of compensators that give a good transient response (the measure of how fast the regulation loop responds to a load step and brings the output voltage back to its steady state voltage): 1. if 1/2 c out esr > ? f s use a double pole-double zero, pid or type iii compensator. this is ty pically used for low esr ceramic output capacitor designs. 2. if 1/2 c out esr < fco < ? f s . use a pole zero pair, pi or type ii compensator. this is typically used for tantalum or electrolytic output capacitor designs. compensator this section consists of the feedback resistors, error amplifier, compensation network and reference. it acts to sample the output voltage and create a frequency compensated error signal proportional to the difference between the output voltage and the reference. as this is a negative feedback system, this stage introduces a dc phase shift of 180 degrees. the output of the compensator is then fed into the modulator. what is meant by frequency compensated is that it adds phase and gain where it is lost in the power stage and also acts to ensure gain is low at high frequencies to reduce susceptibility to switching noise. the goal of the compensation network is to achieve a closed loop system that has sufficient phase margin and/or gain margin to ensure system stability across all micrel, inc. mic2150 august 2009 18 m9999-082809-a (408) 944-0800 operating conditions. the detailed analysis for achieving this is covered in other texts and will not be covered here. the following is a method for calculating the correct values for stability. ceramic output capacitor designs the closed loop bode plot response for a correctly compensated ceramic output capacitor design is shown below. figure 11. ceramic output capacitor bode plot the power inductor and output capacitor create the resonant frequency at fo. it is preferred to make the desired crossover frequency (loop bandwidth) greater than this at fco with a phase margin (pm) of typically 50 degrees. the maximum phase boost, on a log scale, occurs approximately half way between the highest zero (fz2) and the lowest pole (fp1). to be precise, it is at 1fp2fz . the required compensation network for this is a double pole, double zero or type iii network shown in figure 12. figure 12. type iii compensation network placement of the 2 poles and 2 zeros choose a loop bandwidth/crossover frequency (fco) at less than one fifth switching frequency and a phase margin (typically 50 degrees will ensure system stability over all conditions). fco < fs/5 pm = 50 degrees place the two phase boost break frequencies such that our maximum phase boost occurs at the desired crossover frequency fco. )pm(sin1 )pm(sin1 fco2fz + ? = )pm(sin1 )pm(sin1 fco1fp ? + = fz1 must be somewhere below or equal to fz2. placing it at one half fz2 helps to spread the frequency range of the phase boost. 22fz1fz / = finally, place the noise suppression pole at one half the switching frequency. 2 f 2fp s = the calculation of the required components to achieve fp1, fp2, fz1 and fz2 for this circuit is ideal for a spreadsheet which is available on the micrel website. however, they can also be calculated using the following method: collect all known circuit parameters l: inductor value c out : output capacitor value esr: output capacitor esr. fco: desired crossover frequency v ramp : internal ramp voltage = 1.5v v ref : internal reference voltage = 0.7v v in : maximum input voltage of the converter calculating network values out cl2 1 fo = choose rc1 value: this can be any reasonable value up to 10k , but in order to keep the values of r1 and c2 within practical limits, this ?factor? can be useful. rc1 = 25k/fo 1fz1rc2 1 1c = 2fp1rc2 1 2c = micrel, inc. mic2150 august 2009 19 m9999-082809-a (408) 944-0800 ramp in out v v 1rc clfco2 3c = 1fp3c2 1 3r = ref out ref vv v1r 2r ? = 3r 2fz3c2 1 1r ? = tantalum/electrolytic ou tput capacitor designs figure 14. type ii compensation network the closed loop bode plot response of the higher esr capacitor design looks something like the figure below. pole and zero positioning out cl2 1 fo = to introduce a boost in phase at and beyond the resonance of the output lc filter (fo), fz can be placed at fo. fz = fo together with phase boost associated with the output capacitor esr zero, this will achieve up to 45 degrees phase margin. the noise suppression pole can be set to one half switching frequency. 2 f fp s = calculating network values figure 13. tantalum output capacitor bode plot choose r1 <10k to reduce susceptibility to noise and inaccuracies induced by the error amplifier bias current. due to the output capacitor esr creating a zero within the range of the desired crossover frequency (fco), this design only requires that one adds one zero and one associated pole. the phase boost in this case occurs between the zero (fz) and the pole (fp) of the compensator. therefore, the zero gain crossover frequency (fco) will be between these two points. the zero is created by rc1 and c1. the pole should be set at one half switching frequency to reduce noise sensitivity. the plateau gain (gain between fz and fp) is set by rc1 and r1, av plateau = rc1/r1, this should be set to a modest gain of five-to-ten to improve transient response. this compensation network is shown in figure 14. r1 = 1k to set output voltage, set r2: ref out ref vv v1r 2r ? = for a plateau gain of 5 51r1rc = fz1rc2 1 1c = assuming fz< micrel, inc. mic2150 august 2009 21 m9999-082809-a (408) 944-0800 ? the output voltage feedback resistors should be placed close to the fb pin. the top side of the upper resistor should connect directly to the output node. run this trace away from the switch node traces and inductor. the bottom side of the lower voltage divider resistor should connect to the gnd pin of the control ic. ? the compensation resistor and capacitors should be placed right next to the comp pin and the other side should connect directly to the gnd pin on the control ic rather than going to the ground plane. ? add placeholders for gate re sistors on the top-side mosfet gate drives. if necessary, gate resistors of 10? or less should be used. micrel, inc. mic2150 august 2009 22 m9999-082809-a (408) 944-0800 mic2150 evaluation board schematic micrel, inc. mic2150 august 2009 23 m9999-082809-a (408) 944-0800 bill of materials item part number manufacturer description qty. c1,c3 tr3d107k016c0100 vishay (1) 100f/16v, d case 2 c8,c10,c11, c12,c20 grm21br61c106ke15l murata (2) or vj0805y106kxxat vishay (1) or 0805yd106k avx (3) 10f/16v, 1210, x5r 5 c13,c14 vj0805y104kxxat vishay (1) 100nf/16v, 0805 2 c7,c28,c29 vj0603y104kxxat vishay (1) 100nf/16v, 0603 3 c6,c9 vj0603y105kxxat vishay (1) 1f/16v, 0603 2 c4,c5 vj0805y105kxxat vishay (1) 1f/16v, 0805 2 c18 c3225x5r0j107m tdk (4) or 12106d107kat2a avx (3) 100f/6.3v, 1210 1 c15 open open, nf 1 c19 tr3d337k6r3c0100 vishay (1) or tpsd337k006r0045 avx (3) 330f/6.3v, d case 1 c21,c22 vj0805y102kxxat vishay (1) 1nf/16v, 0805 2 c26 vj0603a181kxxat vishay (1) 180pf/16v, 0603 1 c25 vj0603a121kxxat vishay (1) 120pf/16v, 0603 1 c23,c24 vj0603y472kxxat vishay (1) 4.7nf/16v, 0603 2 c16,c17 vj0603a220kxxat vishay (1) 22pf/16v, 0603 2 c27 vj0603y222kxxat vishay (1) 2.2nf/16v, 0603 1 c30 open open, nf 1 d1,d2 sd103bws-v-gs08 vishay (1) sd103bws 2 d3,d4 dfls220l-7(not fitted) diodes inc. (5) dfls220l-7 2 l2 hc5-1r5 cooper (6) 1.5h,17a 1 l3 hc5-2r2 cooper (6) 2.2h,14a 1 q1,q4 fdms8680 fairchild (7) or sir462dp vishay (1) 20a hs fet 2 q5,q8 fdms8660as fairchild (7) or si7636dp vishay (1) 20a ls fet 2 q3, q2 not fitted 20a hs fet 0 q7, q6 not fitted 20a ls fet 0 r2,r3,r4 crcw06031002fkea vishay (1) 10k , 0603 3 r18 crcw06034751fkea vishay (1) 4.75k, 0603 1 r17 crcw06031001fkea vishay (1) 1k, 0603 1 r10,r11 crcw06032210fkea vishay (1) 221 ohm, 0603 2 r9,r12 crcw12062r00fkea vishay (1) 2 ohms, 1206 2 r20 crcw06033011fkea vishay (1) 3.01k, 0603 1 r19 crcw06033920fkea vishay (1) 392 ohms, 0603 1 r15 crcw06033651fkea vishay (1) 3.65k, 0603 1 micrel, inc. mic2150 august 2009 24 m9999-082809-a (408) 944-0800 item part number manufacturer description qty. r16 crcw06034991fkea vishay (1) 4.99k, 0603 1 r1 crcw060310r0fkea vishay (1) 10 ohms, 0603 1 r21 crcw06033650fkea vishay (1) 365 ohms , 0603 1 r22 open open, nf 1 u1 mic2150yml micrel semiconductor (8) mic2150 2-phase dual output pwm synchronous buck control ic 1 notes: 1. vishay.: www.vishay.com 2. murata: www.murata.com 3. avx: www.avx.com 4. tdk: www.tdk.com 5. diodes inc.: www.diodes.com 6. cooper electronics: www.cooperet.com 7. fairchild semiconductor: www.fairchildsemi.com 8. micrel, inc.: www.micrel.com micrel, inc. mic2150 august 2009 25 m9999-082809-a (408) 944-0800 recommended layout top copper bottom copper micrel, inc. mic2150 august 2009 26 m9999-082809-a (408) 944-0800 mid layer 1 mid layer 2 micrel, inc. mic2150 august 2009 27 m9999-082809-a (408) 944-0800 package information 24-lead mlf (ml) micrel, inc. 2180 fortune dri ve san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this data sheet is belie ved to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specific ations at any time without notification to the customer. micrel products are not designed or authorized for use as components in life suppor t appliances, devices or systems where malfu nction of a product reasonably be expected to result in pers onal injury. life support devices or systems are devices or systems that (a) are in tended for surgical impla into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. a purchaser?s use or sale of micrel produc ts for use in life support app liances, devices or systems is a purchaser?s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. can nt ? 2009 micrel, incorporated. |
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